module FRM_TOP (
   RESET,

  // interface to global CPU interface
   FRM10G_SCRAME_EN,
   FRM10G_FORCE_RX_LOF,
   FRM10G_FORCE_RX_AIS,
   FRM10G_FORCE_TX_AIS,
   FRM10G_ALM_LOF,
   FRM10G_ALM_OOF,
   FRM10G_PER_B1COUNT,
   FRM10G_PER_B1PULSE,
   FRM10G_FAS_REGKEEP,
  // interface to SFI interface
   FRM_SFI_RCLK_155M,
   FRM_SFI_RDATA,
   FRM_SFI_TCLK_155M,
   FRM_SFI_TDATA,
  //
   FRM_TOH_TDATA,
   FRM_TOH_FCNT8,
   FRM_TOH_FCNT270,
   FRM_TOH_FCNT9,
  //
   FRM_ROH_LOF,
   FRM_ROH_OOF,
   FRM_ROH_FCNT8,
   FRM_ROH_FCNT270,
   FRM_ROH_FCNT9,
   FRM_ROH_RDATA
   );

input                 RESET;

input                 FRM10G_SCRAME_EN;
input                 FRM10G_FORCE_RX_LOF;
input                 FRM10G_FORCE_RX_AIS;
input                 FRM10G_FORCE_TX_AIS;
output reg            FRM10G_ALM_LOF;
output reg            FRM10G_ALM_OOF;
output reg[3:0]       FRM10G_PER_B1COUNT;
output reg            FRM10G_PER_B1PULSE;
input[15:0]           FRM10G_FAS_REGKEEP;

input                 FRM_SFI_RCLK_155M;
input[63:0]           FRM_SFI_RDATA;
input                 FRM_SFI_TCLK_155M;
output[63:0]          FRM_SFI_TDATA;

input[63:0]           FRM_TOH_TDATA;
input[2:0]            FRM_TOH_FCNT8;
input[8:0]            FRM_TOH_FCNT270;
input[3:0]            FRM_TOH_FCNT9;

output                FRM_ROH_LOF;
output                FRM_ROH_OOF;
output[2:0]           FRM_ROH_FCNT8;
output[8:0]           FRM_ROH_FCNT270;
output[3:0]           FRM_ROH_FCNT9;
output[63:0]          FRM_ROH_RDATA;

reg[15:0]             MPI_RX_PAR_KEEP;
reg                   MPI_RX_DSCRM_EN;
reg                   MPI_RX_FORCE_LOF;
reg                   MPI_RX_FORCE_AIS;
(* keep = "TRUE" *)  wire                  MPI_PER_B1PULSE;
(* keep = "TRUE" *)  wire[3:0]             MPI_PER_B1COUNT;
wire                  MPI_RX_ALM_LOF;
wire                  MPI_RX_ALM_OOF;
reg                   MPI_TX_SCRM_EN;
reg                   MPI_TX_FORCE_AIS;

(* keep = "TRUE" *)wire                  MATCH2DSCRM_LOF;
(* keep = "TRUE" *)wire                  MATCH2DSCRM_OOF;
(* keep = "TRUE" *)wire[2:0]             MATCH2DSCRM_FCNT8;
(* keep = "TRUE" *)wire[8:0]             MATCH2DSCRM_FCNT270;
(* keep = "TRUE" *)wire[3:0]             MATCH2DSCRM_FCNT9;
(* keep = "TRUE" *)wire[63:0]            MATCH2DSCRM_DATA;



// clock in CPU control signals with the clock which used for data procedure
  assign  MPI_RX_ALM_LOF =MATCH2DSCRM_LOF;
  assign  MPI_RX_ALM_OOF =MATCH2DSCRM_OOF;
always @( posedge RESET or posedge FRM_SFI_RCLK_155M) begin
   if ( RESET==1'b1 ) begin
      MPI_RX_PAR_KEEP[15:0]                     <= 16'd0;
      MPI_RX_DSCRM_EN                           <= 1'b1;
      MPI_RX_FORCE_LOF                          <= 1'b0;
      MPI_RX_FORCE_AIS                          <= 1'b0;
      FRM10G_PER_B1PULSE                        <= 1'b0;
      FRM10G_PER_B1COUNT[3:0]                   <= 4'd0;
      FRM10G_ALM_LOF                            <= 1'b0;
      FRM10G_ALM_OOF                            <= 1'b0;
   end
   else begin
      MPI_RX_PAR_KEEP[15:0]                     <= FRM10G_FAS_REGKEEP[15:0];
      MPI_RX_DSCRM_EN                           <= FRM10G_SCRAME_EN;
      MPI_RX_FORCE_LOF                          <= FRM10G_FORCE_RX_LOF;
      MPI_RX_FORCE_AIS                          <= FRM10G_FORCE_RX_AIS;
      FRM10G_PER_B1PULSE                        <= MPI_PER_B1PULSE;
      FRM10G_PER_B1COUNT[3:0]                   <= MPI_PER_B1COUNT[3:0];
      FRM10G_ALM_LOF                            <= MPI_RX_ALM_LOF;
      FRM10G_ALM_OOF                            <= MPI_RX_ALM_OOF;
   end
end
always @( posedge RESET or posedge FRM_SFI_TCLK_155M) begin
   if ( RESET==1'b1 ) begin
      MPI_TX_SCRM_EN                            <= 1'b1;
      MPI_TX_FORCE_AIS                          <= 1'b0;
   end
   else begin
      MPI_TX_SCRM_EN                            <= FRM10G_SCRAME_EN;
      MPI_TX_FORCE_AIS                          <= FRM10G_FORCE_TX_AIS;
   end
end





FRM_SCRM              INST_FRM_SCRM(
   .RESET             ( RESET ),
   .TCLK_155M         ( FRM_SFI_TCLK_155M ),

   .DBIN_TDATA        ( FRM_TOH_TDATA[63:0] ),
   .DBIN_FCNT8        ( FRM_TOH_FCNT8[2:0] ),
   .DBIN_FCNT270      ( FRM_TOH_FCNT270[8:0] ),
   .DBIN_FCNT9        ( FRM_TOH_FCNT9[3:0] ),
   .MPI_SRCM_EN       ( MPI_TX_SCRM_EN ),
   .MPI_FORCE_AIS     ( MPI_TX_FORCE_AIS ),

   .DBOUT_TDATA       ( FRM_SFI_TDATA[63:0] )
   );


FRM_FAS_MATCH         INST_FRM_FAS_MATCH(
   .RESET             ( RESET ),

   .RCLK_155M         ( FRM_SFI_RCLK_155M ),
   .SFI4_RDATA        ( FRM_SFI_RDATA[63:0] ),
   .MPI_PAR_KEEP      ( MPI_RX_PAR_KEEP[7:0] ),
   .MPI_FORCE_LOF     ( MPI_RX_FORCE_LOF ),
   .MPI_FORCE_AIS     ( MPI_RX_FORCE_AIS ),

   .FAS_LOF           ( MATCH2DSCRM_LOF ),
   .FAS_OOF           ( MATCH2DSCRM_OOF ),
   .FAS_MATCH_FCNT8   ( MATCH2DSCRM_FCNT8[2:0] ),
   .FAS_MATCH_FCNT270 ( MATCH2DSCRM_FCNT270[8:0] ),
   .FAS_MATCH_FCNT9   ( MATCH2DSCRM_FCNT9[3:0] ),
   .FAS_MATCH_DATA    ( MATCH2DSCRM_DATA[63:0] )
   );

 FRM_DSCRM            INST_FRM_DSCRM(
   .RESET             ( RESET ),
   .RCLK_155M         ( FRM_SFI_RCLK_155M ),
   .MPI_DSCRM_EN      ( MPI_RX_DSCRM_EN ),

   .FAS_LOF           ( MATCH2DSCRM_LOF ),
   .FAS_OOF           ( MATCH2DSCRM_OOF ),
   .FAS_FCNT8         ( MATCH2DSCRM_FCNT8[2:0] ),
   .FAS_FCNT270       ( MATCH2DSCRM_FCNT270[8:0] ),
   .FAS_FCNT9         ( MATCH2DSCRM_FCNT9[3:0] ),
   .FAS_DATA          ( MATCH2DSCRM_DATA[63:0] ),

   .DSCRM_LOF         ( FRM_ROH_LOF ),
   .DSCRM_OOF         ( FRM_ROH_OOF ),
   .DSCRM_FCNT8       ( FRM_ROH_FCNT8[2:0] ),
   .DSCRM_FCNT270     ( FRM_ROH_FCNT270[8:0] ),
   .DSCRM_FCNT9       ( FRM_ROH_FCNT9[3:0] ),
   .DSCRM_DATA        ( FRM_ROH_RDATA[63:0] ),
   .MPI_PER_B1COUNT   ( MPI_PER_B1COUNT[3:0] ),
   .MPI_PER_B1PULSE   ( MPI_PER_B1PULSE )
   );

endmodule 
